1. Field of the Invention
The present invention relates to a bus system and data transfer method therefor, and more particularly, to a bus system including an address/control bus and a data bus that connect a plurality of master devices to a plurality of slave devices, and data transfer method therefor. Korean Patent Application No. 00-43334, filed Jul. 27, 2000, is incorporated herein by reference.
2. Description of the Related Art
An arbiter is used to arbitrate access to a bus. In conventional bus systems, an arbiter receives requests for access to a bus from a plurality of master devices, arbitrates the bus access requests according to a specific arbitration algorithm, and grants control of the bus to the master devices based on the arbitration result. Once a master""s request has been granted, the master may take control of the bus until the master has completed its transfer of data with a corresponding slave device. Here, the bus means both an address/control bus and a data bus. There is substantially no problem in a conventional arbitration system by an arbiter as long as slave devices access both the address/control bus and the data bus concurrently.
However, a currently used bus system adopts a high-speed memory such as synchronous DRAM (SDRAM) as a slave device. In the case of high-speed memory such as SDRAM, it does not access an access/control bus concurrently with a data bus. That is, if an address/control signal such as an address or read/write flag is input to SDRAM, data is output or input after a predetermined latency time has lapsed. Thus, a master device actually takes control of an address/control bus or a data bus for a shorter period than is expected. According to the conventional arbitration system in which access to or control of both address/control bus and data bus is granted simultaneously for a predetermined time, there are a large number of idle clock cycles of the address/control bus and/or data bus, which may degrade the efficiency of bus access.
To solve the above problems, it is an objective of the present invention to provide a bus system having a high speed slave device such as synchronous DRAM (SDRAM) for improving the efficiency of bus access, and a data transfer method therefor.
Accordingly, to achieve the above objectives, the present invention provides a data transfer arbitration method that includes the steps of (a) receiving bus requests from two or more master devices and arbitrating access to an address/control bus according to a predetermined arbitration algorithm, (b) receiving an access command packet containing information for data transfer preparation from the master device through the address/control bus in the order determined as a result of the arbitration and transmitting the received access command packet to a corresponding slave device, (c) receiving notification of transfer preparation completion of corresponding data from the slave device, (d) informing the master device of the start of data transfer, and (e) transferring data through the data bus.
The data transfer method further includes the steps of (f) receiving notification of data transfer completion from the slave device, and (g) informing the master device of data transfer completion.
Preferably, the step (c) includes the step of (c1) receiving a transfer control packet containing a data transfer start indicator and an identifier of a corresponding master device from the slave device, and the step (d) includes the step (d1) of informing the master device having the identifier of the data transfer start.
Preferably, the step (f) includes the step of (f1) receiving a transfer control packet containing a data transfer finish indicator and an identifier of a corresponding master device, and the step (g) includes the step of (g1) informing the master device having the identifier of the data transfer finish.
The access command packet includes an address, a read/write flag, a bit width, an identifier of a master device transmitting the access command packet, and a burst length for burst transmission of data.
If data transfer in the step (e) aborts, the data method includes the steps of (h) receiving the abort indicator from the slave device, (i) informing a corresponding master device of the abort of data transmission, and (j) retransmitting data.
Preferably, the step (h) includes the step of (hxe2x80x2) receiving the abort indicator and an identifier of a corresponding master device from the slave device, and the step (i) includes the step of (ixe2x80x2) transmitting the abort indicator to the master device having the identifier.
The present invention also provides a bus system including an address/control bus and a data bus. The bus system includes an arbiter for arbitrating access to the address/control bus according to a predetermined arbitration algorithm, one or more master devices which transmits an access command packet containing information for data transfer preparation through the address/control bus in the order determined as a result of the arbitration, and which receives or transmits data through the data bus upon receipt of a notice of data transfer start from the arbiter, and one or more slave devices which informs the arbiter of data transfer preparation completion by receiving and executing the access command packet, and which receives or transmits data through the data bus upon receipt of a notice of data transfer start to a corresponding master device from the arbiter.
Preferably, upon receipt of data transfer finish from the slave device, the arbiter informs the master device of the data transfer finish. The slave device transmits a transfer control packet containing a data transfer start indicator and an identifier of a corresponding device for informing about data transfer preparation completion, and the arbiter informs the master device, having the identifier contained in the transfer control packet, of the data transfer start.
Furthermore, the slave device transmits a transfer control packet containing a data transfer finish indicator and an identifier of a corresponding master device, if the data transfer is complete. The access command packet contains an address, a read/write flag, a bit width, an identifier of a master device transmitting the access command packet, and a burst length for burst transmission of data.
Preferably, if data transfer aborts, the slave device transmits a transfer control packet containing the abort indicator and an identifier of a corresponding master device to the arbiter, and the arbiter transmits the abort indicator to the master device having the identifier contained in the transfer control packet.